Difference between revisions of "Plugin:Intel PMU"

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   | Manpage={{Manpage|collectd.conf|5|plugin_intel_pmu}}
 
   | Manpage={{Manpage|collectd.conf|5|plugin_intel_pmu}}
 
}}
 
}}
−
Performance counters are CPU hardware registers that count hardware events such as instructions executed, cache-misses suffered, or branches mispredicted. They form a basis for profiling applications to trace dynamic control flow and identify hotspots. [https://perf.wiki.kernel.org/index.php/Main_Page Linux perf] interface provides rich generalized abstractions over hardware specific capabilities. The ''intel_pmu'' plugin collects performance counters data on Intel CPUs using Linux perf interface. All events are reported on a per core basis.
+
 
 +
The ''intel_pmu plugin'' collects information provided by [https://perf.wiki.kernel.org/index.php/Main_Page Linux perf] interface which  provides rich generalized abstractions over hardware specific capabilities. All events are reported on a per core basis.
 +
 
 +
Performance counters are CPU hardware registers that count hardware events such as instructions executed, cache-misses suffered, or branches mispredicted. They form a basis for profiling applications to trace dynamic control flow and identify hotspots.
 +
 
 
For a full description of available options please refer to the {{Manpage|collectd.conf|5|plugin_intel_pmu}} manual page.
 
For a full description of available options please refer to the {{Manpage|collectd.conf|5|plugin_intel_pmu}} manual page.
  
 
== Synopsis ==
 
== Synopsis ==
−
 
+
{{See|[[Plugin:Intel_PMU/Config]]}}
 
  <Plugin intel_pmu>
 
  <Plugin intel_pmu>
 
     ReportHardwareCacheEvents true
 
     ReportHardwareCacheEvents true
Line 21: Line 25:
 
     HardwareEvents "L2_RQSTS.CODE_RD_HIT,L2_RQSTS.CODE_RD_MISS" "L2_RQSTS.ALL_CODE_RD"
 
     HardwareEvents "L2_RQSTS.CODE_RD_HIT,L2_RQSTS.CODE_RD_MISS" "L2_RQSTS.ALL_CODE_RD"
 
     Cores "0" "1,35" "[12-17]"
 
     Cores "0" "1,35" "[12-17]"
 +
    DispatchMultiPmu false
 
   </Plugin>
 
   </Plugin>
 +
 +
For a full description of available options please refer to the {{Manpage|collectd.conf|5|plugin_intel_pmu}} manual page.
 +
 +
=== Parameters ===
 +
 +
{|class="wikitable"
 +
! Name
 +
! Description
 +
! Comment
 +
|-
 +
| Interval
 +
| The interval within which to retrieve statistics on monitored events in seconds
 +
| Interval option is supported by collectd and is defined in <LoadPlugin> block. No additional functionality should be developed in intel_pmu plugin to support this option.
 +
|-
 +
| ReportHardwareCacheEvents
 +
| Enable/disable monitoring of hardware cache events
 +
|
 +
|-
 +
| ReportKernelPMUEvents
 +
| Enable/disable monitoring of kernel PMU events
 +
|
 +
|-
 +
| ReportSoftwareEvents
 +
| Enable/disable monitoring of software vents
 +
|
 +
|-
 +
| EventList
 +
| Path to hardware events list file for current CPU.
 +
| File can be downloaded by event_download.py script which is part of pmu-tools package.
 +
|-
 +
| HardwareEvents
 +
| String containing comma separated list of hardware specific events to monitor
 +
|
 +
|-
 +
| Cores
 +
| Core groups definition. Monitored metrics are reported only for configured cores. If this option is omitted all available cores are monitored.
 +
If a group is enclosed in square brackets each core is added individually to a separate group (that is statistics are not aggregated).
 +
| Allowed formats:
 +
"0,1,2,3"
 +
"0-3"
 +
"[0-3]"
 +
|-
 +
| DispatchMultiPmu
 +
| Enable/disable dispatching of cloned multi PMU for uncore events. If disabled only total sum is dispatched as single event. If enabled separate metric is dispatched for every counter.
 +
| Allowed values: true or false
 +
Uncore event example: UNC_CHA_DIR_LOOKUP.NO_SNP.
 +
If enabled information about event type is added to type_instance, e.g.: "UNC_CHA_DIR_LOOKUP.NO_SNP:type=30". It allows to distinguish between multiple counters for one event.
 +
|}
 +
 +
== Metrics ==
 +
 +
{| class="wikitable"
 +
|-
 +
! <br />Metric/<br />  <br />Feature/Input
 +
! <br />Name
 +
! <br />Date Type
 +
! <br />Format Example
 +
! <br />Description
 +
! <br />Dependencies
 +
! <br />Limitations
 +
! <br />Comments
 +
|-
 +
| <br />Metric
 +
| <br />L1-dcache-loads
 +
| <br />Integer
 +
| <br />23734
 +
| <br />Level 1 cache for  data (L1d) read accesses by a CPU core
 +
| <br />jevents from  pmu-tools
 +
| <br />
 +
| <br />Dependent on  jevents library to read the metric value
 +
|-
 +
| <br />Metric
 +
| <br />L1-dcache-load-misses
 +
| <br />Integer
 +
| <br />23734
 +
| <br />Level 1 cache for  data (L1d) read misses by a CPU core
 +
| <br />jevents from  pmu-tools
 +
| <br />
 +
| <br />Dependent on  jevents library to read the metric value
 +
|-
 +
| <br />Metric
 +
| <br />L1-dcache-stores
 +
| <br />Integer
 +
| <br />23734
 +
| <br />Level 1 cache for  data (L1d) writes by a CPU core
 +
| <br />jevents from  pmu-tools
 +
| <br />
 +
| <br />Dependent on  jevents library to read the metric value
 +
|-
 +
| <br />Metric
 +
| <br />L1-dcache-store-misses
 +
| <br />Integer
 +
| <br />23734
 +
| <br />Level 1 cache for  data (L1d) write misses by a CPU core
 +
| <br />jevents from  pmu-tools
 +
| <br />
 +
| <br />Dependent on  jevents library to read the metric value
 +
|-
 +
| <br />Metric
 +
| <br />L1-dcache-prefetches
 +
| <br />Integer
 +
| <br />23734
 +
| <br />Level 1 cache for  data (L1d) prefetch accesses by a CPU core
 +
| <br />jevents from  pmu-tools
 +
| <br />
 +
| <br />Dependent on  jevents library to read the metric value
 +
|-
 +
| <br />Metric
 +
| <br />L1-dcache-prefetch-misses
 +
| <br />Integer
 +
| <br />23734
 +
| <br />Level 1 cache for  data (L1d) prefetch misses by a CPU core
 +
| <br />jevents from  pmu-tools
 +
| <br />
 +
| <br />Dependent on  jevents library to read the metric value
 +
|-
 +
| <br />Metric
 +
| <br />L1-icache-loads
 +
| <br />Integer
 +
| <br />23734
 +
| <br />Level 1 cache for  instructions (L1i) read accesses by a CPU core
 +
| <br />jevents from  pmu-tools
 +
| <br />
 +
| <br />Dependent on  jevents library to read the metric value
 +
|-
 +
| <br />Metric
 +
| <br />L1-icache-load-misses
 +
| <br />Integer
 +
| <br />23734
 +
| <br />Level 1 cache for  instructions (L1i) read misses by a CPU core
 +
| <br />jevents from  pmu-tools
 +
| <br />
 +
| <br />Dependent on  jevents library to read the metric value
 +
|-
 +
| <br />Metric
 +
| <br />L1-icache-prefetches
 +
| <br />Integer
 +
| <br />23734
 +
| <br />Level 1 cache for  instructions (L1i) prefetch accesses by a CPU core
 +
| <br />jevents from  pmu-tools
 +
| <br />
 +
| <br />Dependent on  jevents library to read the metric value
 +
|-
 +
| <br />Metric
 +
| <br />L1-icache-prefetch-misses
 +
| <br />Integer
 +
| <br />23734
 +
| <br />Level 1 cache for  instructions (L1i) prefetch misses by a CPU core
 +
| <br />jevents from  pmu-tools
 +
| <br />
 +
| <br />Dependent on  jevents library to read the metric value
 +
|-
 +
| <br />Metric
 +
| <br />LLC-loads
 +
| <br />Integer
 +
| <br />23734
 +
| <br />Last level cache  (LLC) read accesses by a CPU core
 +
| <br />jevents from  pmu-tools
 +
| <br />
 +
| <br />Dependent on  jevents library to read the metric value
 +
|-
 +
| <br />Metric
 +
| <br />LLC-load-misses
 +
| <br />Integer
 +
| <br />23734
 +
| <br />Last level cache  (LLC) read misses by a CPU core
 +
| <br />jevents from  pmu-tools
 +
| <br />
 +
| <br />Dependent on  jevents library to read the metric value
 +
|-
 +
| <br />Metric
 +
| <br />LLC-stores
 +
| <br />Integer
 +
| <br />23734
 +
| <br />Last level cache  (LLC) writes by a CPU core
 +
| <br />jevents from  pmu-tools
 +
| <br />
 +
| <br />Dependent on  jevents library to read the metric value
 +
|-
 +
| <br />Metric
 +
| <br />LLC-store-misses
 +
| <br />Integer
 +
| <br />23734
 +
| <br />Last level cache  (LLC) write misses by a CPU core
 +
| <br />jevents from  pmu-tools
 +
| <br />
 +
| <br />Dependent on  jevents library to read the metric value
 +
|-
 +
| <br />Metric
 +
| <br />LLC-prefetches
 +
| <br />Integer
 +
| <br />23734
 +
| <br />Last level cache  (LLC) prefetch accesses by a CPU core
 +
| <br />jevents from  pmu-tools
 +
| <br />
 +
| <br />Dependent on  jevents library to read the metric value
 +
|-
 +
| <br />Metric
 +
| <br />LLC-prefetch-misses
 +
| <br />Integer
 +
| <br />23734
 +
| <br />Last level cache  (LLC) prefetch misses by a CPU core
 +
| <br />jevents from  pmu-tools
 +
| <br />
 +
| <br />Dependent on  jevents library to read the metric value
 +
|-
 +
| <br />Metric
 +
| <br />dTLB-loads
 +
| <br />Integer
 +
| <br />23734
 +
| <br />Translation  lookaside buffer for data (dTLB) read accesses by a CPU core
 +
| <br />jevents from  pmu-tools
 +
| <br />
 +
| <br />Dependent on  jevents library to read the metric value
 +
|-
 +
| <br />Metric
 +
| <br />dTLB-load-misses
 +
| <br />Integer
 +
| <br />23734
 +
| <br />Translation  lookaside buffer for data (dTLB) read misses by a CPU core
 +
| <br />jevents from  pmu-tools
 +
| <br />
 +
| <br />Dependent on  jevents library to read the metric value
 +
|-
 +
| <br />Metric
 +
| <br />dTLB-stores
 +
| <br />Integer
 +
| <br />23734
 +
| <br />Translation  lookaside buffer for data (dTLB) writes by a CPU core
 +
| <br />jevents from  pmu-tools
 +
| <br />
 +
| <br />Dependent on  jevents library to read the metric value
 +
|-
 +
| <br />Metric
 +
| <br />dTLB-store-misses
 +
| <br />Integer
 +
| <br />23734
 +
| <br />Translation  lookaside buffer for data (dTLB) write misses by a CPU core
 +
| <br />jevents from  pmu-tools
 +
| <br />
 +
| <br />Dependent on  jevents library to read the metric value
 +
|-
 +
| <br />Metric
 +
| <br />dTLB-prefetches
 +
| <br />Integer
 +
| <br />23734
 +
| <br />Translation  lookaside buffer for data (dTLB) prefetch accesses by a CPU core
 +
| <br />jevents from  pmu-tools
 +
| <br />
 +
| <br />Dependent on  jevents library to read the metric value
 +
|-
 +
| <br />Metric
 +
| <br />dTLB-prefetch-misses
 +
| <br />Integer
 +
| <br />23734
 +
| <br />Translation  lookaside buffer for data (dTLB) prefetch misses by a CPU core
 +
| <br />jevents from  pmu-tools
 +
| <br />
 +
| <br />Dependent on  jevents library to read the metric value
 +
|-
 +
| <br />Metric
 +
| <br />iTLB-loads
 +
| <br />Integer
 +
| <br />23734
 +
| <br />Translation  lookaside buffer for instructions (iTLB) read accesses by a CPU core
 +
| <br />jevents from  pmu-tools
 +
| <br />
 +
| <br />Dependent on  jevents library to read the metric value
 +
|-
 +
| <br />Metric
 +
| <br />iTLB-load-misses
 +
| <br />Integer
 +
| <br />23734
 +
| <br />Translation  lookaside buffer for instructions (iTLB) read misses by a CPU core
 +
| <br />jevents from  pmu-tools
 +
| <br />
 +
| <br />Dependent on  jevents library to read the metric value
 +
|-
 +
| <br />Metric
 +
| <br />branch-loads
 +
| <br />Integer
 +
| <br />23734
 +
| <br />Branch prediction  unit read accesses by a CPU core
 +
| <br />jevents from  pmu-tools
 +
| <br />
 +
| <br />Dependent on  jevents library to read the metric value
 +
|-
 +
| <br />Metric
 +
| <br />branch-load-misses
 +
| <br />Integer
 +
| <br />23734
 +
| <br />Branch prediction  unit read misses by a CPU core
 +
| <br />jevents from  pmu-tools
 +
| <br />
 +
| <br />Dependent on  jevents library to read the metric value
 +
|-
 +
| <br />Metric
 +
| <br />cpu-cycles
 +
| <br />Integer
 +
| <br />23734
 +
| <br />Total CPU cycles  by a CPU core
 +
| <br />jevents from  pmu-tools
 +
| <br />
 +
| <br />Dependent on  jevents library to read the metric value
 +
|-
 +
| <br />Metric
 +
| <br />instructions
 +
| <br />Integer
 +
| <br />23734
 +
| <br />Retired  instructions by a CPU core
 +
| <br />jevents from  pmu-tools
 +
| <br />Note: these can be  affected by various issues, most notably hardware interrupt counts.
 +
| <br />Dependent on  jevents library to read the metric value
 +
|-
 +
| <br />Metric
 +
| <br />cache-references
 +
| <br />Integer
 +
| <br />23734
 +
| <br />Cache accesses per  CPU core. Usually this indicates Last Level Cache accesses but this may vary  depending on CPU type.
 +
| <br />jevents from  pmu-tools
 +
| <br />
 +
| <br />Dependent on  jevents library to read the metric value
 +
|-
 +
| <br />Metric
 +
| <br />cache-misses
 +
| <br />Integer
 +
| <br />23734
 +
| <br />Cache read misses  by a CPU core. Usually this indicates Last Level Cache misses.
 +
| <br />jevents from  pmu-tools
 +
| <br />
 +
| <br />Dependent on  jevents library to read the metric value
 +
|-
 +
| <br />Metric
 +
| <br />branches
 +
| <br />Integer
 +
| <br />23734
 +
| <br />Retired branch  instructions by a CPU core
 +
| <br />jevents from  pmu-tools
 +
| <br />
 +
| <br />Dependent on  jevents library to read the metric value
 +
|-
 +
| <br />Metric
 +
| <br />branch-misses
 +
| <br />Integer
 +
| <br />23734
 +
| <br />Mispredicted  branch instructions by a CPU core
 +
| <br />jevents from  pmu-tools
 +
| <br />
 +
| <br />Dependent on  jevents library to read the metric value
 +
|-
 +
| <br />Metric
 +
| <br />bus-cycles
 +
| <br />Integer
 +
| <br />23734
 +
| <br />Bus cycles per CPU  core, which can be different from total cycles.
 +
| <br />jevents from  pmu-tools
 +
| <br />
 +
| <br />Dependent on  jevents library to read the metric value
 +
|-
 +
| <br />Metric
 +
| <br />cpu-clock
 +
| <br />Integer
 +
| <br />23734
 +
| <br />Reports the CPU  clock, a high-resolution per-CPU timer, by a CPU core. Software event  provided by the kernel.
 +
| <br />jevents from  pmu-tools
 +
| <br />
 +
| <br />Dependent on  jevents library to read the metric value
 +
|-
 +
| <br />Metric
 +
| <br />task-clock
 +
| <br />Integer
 +
| <br />23734
 +
| <br />Reports a clock  count specific to the task that is running, by a CPU core. Software event  provided by the kernel.
 +
| <br />jevents from  pmu-tools
 +
| <br />
 +
| <br />Dependent on  jevents library to read the metric value
 +
|-
 +
| <br />Metric
 +
| <br />context-switches
 +
| <br />Integer
 +
| <br />23734
 +
| <br />Number of context  switches per CPU core. Software event provided by the kernel.
 +
| <br />jevents from  pmu-tools
 +
| <br />
 +
| <br />Dependent on  jevents library to read the metric value
 +
|-
 +
| <br />Metric
 +
| <br />cpu-migrations
 +
| <br />Integer
 +
| <br />23734
 +
| <br />Number of times  the process has migrated to a new CPU, by a CPU core. Software event provided  by the kernel.
 +
| <br />jevents from  pmu-tools
 +
| <br />
 +
| <br />Dependent on  jevents library to read the metric value
 +
|-
 +
| <br />Metric
 +
| <br />page-faults
 +
| <br />Integer
 +
| <br />23734
 +
| <br />Number of page  faults by a CPU core. Software event provided by the kernel.
 +
| <br />jevents from  pmu-tools
 +
| <br />
 +
| <br />Dependent on  jevents library to read the metric value
 +
|-
 +
| <br />Metric
 +
| <br />minor-faults
 +
| <br />Integer
 +
| <br />23734
 +
| <br />Number of minor  page faults by a CPU core. Software event provided by the kernel.
 +
| <br />jevents from  pmu-tools
 +
| <br />
 +
| <br />Dependent on  jevents library to read the metric value
 +
|-
 +
| <br />Metric
 +
| <br />major-faults
 +
| <br />Integer
 +
| <br />23734
 +
| <br />Number of major  page faults by a CPU core. Software event provided by the kernel.
 +
| <br />jevents from  pmu-tools
 +
| <br />
 +
| <br />Dependent on  jevents library to read the metric value
 +
|-
 +
| <br />Metric
 +
| <br />alignment-faults
 +
| <br />Integer
 +
| <br />23734
 +
| <br />Number of  alignment faults by a CPU core. These happen when unaligned memory accesses  happen. Software event provided by the kernel.
 +
| <br />jevents from  pmu-tools
 +
| <br />
 +
| <br />Dependent on  jevents library to read the metric value
 +
|-
 +
| <br />Metric
 +
| <br />emulation-faults
 +
| <br />Integer
 +
| <br />23734
 +
| <br />Number of  emulation faults by a CPU core. The kernel sometimes traps on unimplemented  instructions and emulates them for user space. Software event provided by the  kernel.
 +
| <br />jevents from  pmu-tools
 +
| <br />
 +
| <br />Dependent on  jevents library to read the metric value
 +
|-
 +
| <br />Input
 +
| <br />Cores
 +
| <br />Integer Array as  String
 +
| <br />"[0-12]"  or "1,2,3"
 +
| <br />The list of CPU  core(s) to be provided as input by the user for which the corresponding  metrics are required
 +
| <br />None
 +
| <br />None
 +
| <br />Configuration  input in the plugin .conf file
 +
|-
 +
| <br />Input
 +
| <br />Configuration  Interval
 +
| <br />Integer
 +
| <br />1 or 10
 +
| <br />The interval in  seconds at which the metrics need to be collectd
 +
| <br />None
 +
| <br />None
 +
| <br />Configuration  input in the plugin .conf file
 +
|-
 +
| <br />Input
 +
| <br />Report Hardware  Cache Events
 +
| <br />Boolean
 +
| <br />true/false
 +
| <br />Report hardware  CPU cache events, list in comments
 +
| <br />None
 +
| <br />None
 +
| <br />L1-dcache-loads,  L1-dcache-load-misses, L1-dcache-stores, L1-dcache-store-misses,  L1-dcache-prefetches, L1-dcache-prefetch-misses, L1-icache-loads,  L1-icache-load-misses, L1-icache-prefetches, L1-icache-prefetch-misses,  LLC-loads, LLC-load-misses, LLC-stores, LLC-store-misses, LLC-prefetches,  LLC-prefetch-misses, dTLB-loads, dTLB-load-misses, dTLB-stores,  dTLB-store-misses, dTLB-prefetches, dTLB-prefetch-misses, iTLB-loads,  iTLB-load-misses, branch-loads, branch-load-misses
 +
|-
 +
| <br />Input
 +
| <br />Report Kernel PMU  Events
 +
| <br />Boolean
 +
| <br />true/false
 +
| <br />Report generalized  hardware CPU events. Not all of these are available on all platforms. List in  comments.
 +
| <br />None
 +
| <br />None
 +
| <br />cpu-cycles,  instructions, cache-references, cache-misses, branches, branch-misses,  bus-cycles
 +
|-
 +
| <br />Input
 +
| <br />Report Software  Events
 +
| <br />Boolean
 +
| <br />true/false
 +
| <br />Software events  provided by the kernel. List in comments.
 +
| <br />None
 +
| <br />None
 +
| <br />cpu-clock,  task-clock, context-switches, cpu-migrations, page-faults, minor-faults,  major-faults, alignment-faults, emulation-faults
 +
|-
 +
| <br />Input
 +
| <br />Event List
 +
| <br />String
 +
| <br />"pmu-events/GenuineIntel-6-55-core.json"
 +
| <br />Path to file with  custom hardware events. The should containt description and definition for  events available for given CPU type.
 +
| <br />None
 +
| <br />File should be  valid for supported CPU type.
 +
| <br />Valid file for  current CPU type can be obtained with use of event_download tool: https://raw.githubusercontent.com/andikleen/pmu-tools/master/event_download.py
 +
|-
 +
| <br />Input
 +
| <br />Hardware Events
 +
| <br />String Array
 +
| <br />L2_RQSTS.CODE_RD_HIT,L2_RQSTS.CODE_RD_MISS
 +
| <br />Custom hardware  events for given CPU type. Names of events must be available in "Event  List" json file.
 +
| <br />event_download.py  tool
 +
| <br />No
 +
| <br />If there are more  events than counters, the kernel uses time multiplexing. With multiplexing,  at the end of the run, the counter is scaled basing on total time enabled vs  time running.
 +
|}
 +
  
 
== Example graph ==
 
== Example graph ==
Line 31: Line 540:
 
== History ==
 
== History ==
  
−
''Cores'' option is available since [https://collectd.org/wiki/index.php?title=Version_5.8 release 5.8.1].
+
* ''Cores'' option is available since [https://collectd.org/wiki/index.php?title=Version_5.8 release 5.8.1].
 +
* Support for uncore multi pmu was added in {{Version|5.11}}
  
 
== Dependencies ==
 
== Dependencies ==
  
 
* [https://github.com/andikleen/pmu-tools/tree/master/jevents jevents]
 
* [https://github.com/andikleen/pmu-tools/tree/master/jevents jevents]
 +
 +
== See also ==
 +
 +
* [[Plugin:Intel_PMU/tests]]
 +
* [https://wiki.opnfv.org/display/fastpath/PMU PMU plugin high level design document]
  
 
[[Category:Plugins]]
 
[[Category:Plugins]]
 
{{DEFAULTSORT:Intel_PMU}}
 
{{DEFAULTSORT:Intel_PMU}}

Latest revision as of 12:39, 27 August 2020

Intel PMU plugin
Type: read
Callbacks: config, init, read, shutdown
Status: supported
First version: 5.8
Copyright: 2017–2018 Intel Corporation
License: MIT license
Manpage: collectd.conf(5)
List of Plugins

The intel_pmu plugin collects information provided by Linux perf interface which provides rich generalized abstractions over hardware specific capabilities. All events are reported on a per core basis.

Performance counters are CPU hardware registers that count hardware events such as instructions executed, cache-misses suffered, or branches mispredicted. They form a basis for profiling applications to trace dynamic control flow and identify hotspots.

For a full description of available options please refer to the collectd.conf(5) manual page.

Synopsis

→ See: Plugin:Intel_PMU/Config
<Plugin intel_pmu>
   ReportHardwareCacheEvents true
   ReportKernelPMUEvents true
   ReportSoftwareEvents true
   EventList "/var/cache/pmu/GenuineIntel-6-2D-core.json"
   HardwareEvents "L2_RQSTS.CODE_RD_HIT,L2_RQSTS.CODE_RD_MISS" "L2_RQSTS.ALL_CODE_RD"
   Cores "0" "1,35" "[12-17]"
   DispatchMultiPmu false
 </Plugin>

For a full description of available options please refer to the collectd.conf(5) manual page.

Parameters

Name Description Comment
Interval The interval within which to retrieve statistics on monitored events in seconds Interval option is supported by collectd and is defined in <LoadPlugin> block. No additional functionality should be developed in intel_pmu plugin to support this option.
ReportHardwareCacheEvents Enable/disable monitoring of hardware cache events
ReportKernelPMUEvents Enable/disable monitoring of kernel PMU events
ReportSoftwareEvents Enable/disable monitoring of software vents
EventList Path to hardware events list file for current CPU. File can be downloaded by event_download.py script which is part of pmu-tools package.
HardwareEvents String containing comma separated list of hardware specific events to monitor
Cores Core groups definition. Monitored metrics are reported only for configured cores. If this option is omitted all available cores are monitored.

If a group is enclosed in square brackets each core is added individually to a separate group (that is statistics are not aggregated).

Allowed formats:

"0,1,2,3" "0-3" "[0-3]"

DispatchMultiPmu Enable/disable dispatching of cloned multi PMU for uncore events. If disabled only total sum is dispatched as single event. If enabled separate metric is dispatched for every counter. Allowed values: true or false

Uncore event example: UNC_CHA_DIR_LOOKUP.NO_SNP. If enabled information about event type is added to type_instance, e.g.: "UNC_CHA_DIR_LOOKUP.NO_SNP:type=30". It allows to distinguish between multiple counters for one event.

Metrics


Metric/

Feature/Input
Name
Date Type
Format Example
Description
Dependencies
Limitations
Comments

Metric
L1-dcache-loads
Integer
23734
Level 1 cache for data (L1d) read accesses by a CPU core
jevents from pmu-tools

Dependent on jevents library to read the metric value

Metric
L1-dcache-load-misses
Integer
23734
Level 1 cache for data (L1d) read misses by a CPU core
jevents from pmu-tools

Dependent on jevents library to read the metric value

Metric
L1-dcache-stores
Integer
23734
Level 1 cache for data (L1d) writes by a CPU core
jevents from pmu-tools

Dependent on jevents library to read the metric value

Metric
L1-dcache-store-misses
Integer
23734
Level 1 cache for data (L1d) write misses by a CPU core
jevents from pmu-tools

Dependent on jevents library to read the metric value

Metric
L1-dcache-prefetches
Integer
23734
Level 1 cache for data (L1d) prefetch accesses by a CPU core
jevents from pmu-tools

Dependent on jevents library to read the metric value

Metric
L1-dcache-prefetch-misses
Integer
23734
Level 1 cache for data (L1d) prefetch misses by a CPU core
jevents from pmu-tools

Dependent on jevents library to read the metric value

Metric
L1-icache-loads
Integer
23734
Level 1 cache for instructions (L1i) read accesses by a CPU core
jevents from pmu-tools

Dependent on jevents library to read the metric value

Metric
L1-icache-load-misses
Integer
23734
Level 1 cache for instructions (L1i) read misses by a CPU core
jevents from pmu-tools

Dependent on jevents library to read the metric value

Metric
L1-icache-prefetches
Integer
23734
Level 1 cache for instructions (L1i) prefetch accesses by a CPU core
jevents from pmu-tools

Dependent on jevents library to read the metric value

Metric
L1-icache-prefetch-misses
Integer
23734
Level 1 cache for instructions (L1i) prefetch misses by a CPU core
jevents from pmu-tools

Dependent on jevents library to read the metric value

Metric
LLC-loads
Integer
23734
Last level cache (LLC) read accesses by a CPU core
jevents from pmu-tools

Dependent on jevents library to read the metric value

Metric
LLC-load-misses
Integer
23734
Last level cache (LLC) read misses by a CPU core
jevents from pmu-tools

Dependent on jevents library to read the metric value

Metric
LLC-stores
Integer
23734
Last level cache (LLC) writes by a CPU core
jevents from pmu-tools

Dependent on jevents library to read the metric value

Metric
LLC-store-misses
Integer
23734
Last level cache (LLC) write misses by a CPU core
jevents from pmu-tools

Dependent on jevents library to read the metric value

Metric
LLC-prefetches
Integer
23734
Last level cache (LLC) prefetch accesses by a CPU core
jevents from pmu-tools

Dependent on jevents library to read the metric value

Metric
LLC-prefetch-misses
Integer
23734
Last level cache (LLC) prefetch misses by a CPU core
jevents from pmu-tools

Dependent on jevents library to read the metric value

Metric
dTLB-loads
Integer
23734
Translation lookaside buffer for data (dTLB) read accesses by a CPU core
jevents from pmu-tools

Dependent on jevents library to read the metric value

Metric
dTLB-load-misses
Integer
23734
Translation lookaside buffer for data (dTLB) read misses by a CPU core
jevents from pmu-tools

Dependent on jevents library to read the metric value

Metric
dTLB-stores
Integer
23734
Translation lookaside buffer for data (dTLB) writes by a CPU core
jevents from pmu-tools

Dependent on jevents library to read the metric value

Metric
dTLB-store-misses
Integer
23734
Translation lookaside buffer for data (dTLB) write misses by a CPU core
jevents from pmu-tools

Dependent on jevents library to read the metric value

Metric
dTLB-prefetches
Integer
23734
Translation lookaside buffer for data (dTLB) prefetch accesses by a CPU core
jevents from pmu-tools

Dependent on jevents library to read the metric value

Metric
dTLB-prefetch-misses
Integer
23734
Translation lookaside buffer for data (dTLB) prefetch misses by a CPU core
jevents from pmu-tools

Dependent on jevents library to read the metric value

Metric
iTLB-loads
Integer
23734
Translation lookaside buffer for instructions (iTLB) read accesses by a CPU core
jevents from pmu-tools

Dependent on jevents library to read the metric value

Metric
iTLB-load-misses
Integer
23734
Translation lookaside buffer for instructions (iTLB) read misses by a CPU core
jevents from pmu-tools

Dependent on jevents library to read the metric value

Metric
branch-loads
Integer
23734
Branch prediction unit read accesses by a CPU core
jevents from pmu-tools

Dependent on jevents library to read the metric value

Metric
branch-load-misses
Integer
23734
Branch prediction unit read misses by a CPU core
jevents from pmu-tools

Dependent on jevents library to read the metric value

Metric
cpu-cycles
Integer
23734
Total CPU cycles by a CPU core
jevents from pmu-tools

Dependent on jevents library to read the metric value

Metric
instructions
Integer
23734
Retired instructions by a CPU core
jevents from pmu-tools
Note: these can be affected by various issues, most notably hardware interrupt counts.
Dependent on jevents library to read the metric value

Metric
cache-references
Integer
23734
Cache accesses per CPU core. Usually this indicates Last Level Cache accesses but this may vary depending on CPU type.
jevents from pmu-tools

Dependent on jevents library to read the metric value

Metric
cache-misses
Integer
23734
Cache read misses by a CPU core. Usually this indicates Last Level Cache misses.
jevents from pmu-tools

Dependent on jevents library to read the metric value

Metric
branches
Integer
23734
Retired branch instructions by a CPU core
jevents from pmu-tools

Dependent on jevents library to read the metric value

Metric
branch-misses
Integer
23734
Mispredicted branch instructions by a CPU core
jevents from pmu-tools

Dependent on jevents library to read the metric value

Metric
bus-cycles
Integer
23734
Bus cycles per CPU core, which can be different from total cycles.
jevents from pmu-tools

Dependent on jevents library to read the metric value

Metric
cpu-clock
Integer
23734
Reports the CPU clock, a high-resolution per-CPU timer, by a CPU core. Software event provided by the kernel.
jevents from pmu-tools

Dependent on jevents library to read the metric value

Metric
task-clock
Integer
23734
Reports a clock count specific to the task that is running, by a CPU core. Software event provided by the kernel.
jevents from pmu-tools

Dependent on jevents library to read the metric value

Metric
context-switches
Integer
23734
Number of context switches per CPU core. Software event provided by the kernel.
jevents from pmu-tools

Dependent on jevents library to read the metric value

Metric
cpu-migrations
Integer
23734
Number of times the process has migrated to a new CPU, by a CPU core. Software event provided by the kernel.
jevents from pmu-tools

Dependent on jevents library to read the metric value

Metric
page-faults
Integer
23734
Number of page faults by a CPU core. Software event provided by the kernel.
jevents from pmu-tools

Dependent on jevents library to read the metric value

Metric
minor-faults
Integer
23734
Number of minor page faults by a CPU core. Software event provided by the kernel.
jevents from pmu-tools

Dependent on jevents library to read the metric value

Metric
major-faults
Integer
23734
Number of major page faults by a CPU core. Software event provided by the kernel.
jevents from pmu-tools

Dependent on jevents library to read the metric value

Metric
alignment-faults
Integer
23734
Number of alignment faults by a CPU core. These happen when unaligned memory accesses happen. Software event provided by the kernel.
jevents from pmu-tools

Dependent on jevents library to read the metric value

Metric
emulation-faults
Integer
23734
Number of emulation faults by a CPU core. The kernel sometimes traps on unimplemented instructions and emulates them for user space. Software event provided by the kernel.
jevents from pmu-tools

Dependent on jevents library to read the metric value

Input
Cores
Integer Array as String
"[0-12]" or "1,2,3"
The list of CPU core(s) to be provided as input by the user for which the corresponding metrics are required
None
None
Configuration input in the plugin .conf file

Input
Configuration Interval
Integer
1 or 10
The interval in seconds at which the metrics need to be collectd
None
None
Configuration input in the plugin .conf file

Input
Report Hardware Cache Events
Boolean
true/false
Report hardware CPU cache events, list in comments
None
None
L1-dcache-loads, L1-dcache-load-misses, L1-dcache-stores, L1-dcache-store-misses, L1-dcache-prefetches, L1-dcache-prefetch-misses, L1-icache-loads, L1-icache-load-misses, L1-icache-prefetches, L1-icache-prefetch-misses, LLC-loads, LLC-load-misses, LLC-stores, LLC-store-misses, LLC-prefetches, LLC-prefetch-misses, dTLB-loads, dTLB-load-misses, dTLB-stores, dTLB-store-misses, dTLB-prefetches, dTLB-prefetch-misses, iTLB-loads, iTLB-load-misses, branch-loads, branch-load-misses

Input
Report Kernel PMU Events
Boolean
true/false
Report generalized hardware CPU events. Not all of these are available on all platforms. List in comments.
None
None
cpu-cycles, instructions, cache-references, cache-misses, branches, branch-misses, bus-cycles

Input
Report Software Events
Boolean
true/false
Software events provided by the kernel. List in comments.
None
None
cpu-clock, task-clock, context-switches, cpu-migrations, page-faults, minor-faults, major-faults, alignment-faults, emulation-faults

Input
Event List
String
"pmu-events/GenuineIntel-6-55-core.json"
Path to file with custom hardware events. The should containt description and definition for events available for given CPU type.
None
File should be valid for supported CPU type.
Valid file for current CPU type can be obtained with use of event_download tool: https://raw.githubusercontent.com/andikleen/pmu-tools/master/event_download.py

Input
Hardware Events
String Array
L2_RQSTS.CODE_RD_HIT,L2_RQSTS.CODE_RD_MISS
Custom hardware events for given CPU type. Names of events must be available in "Event List" json file.
event_download.py tool
No
If there are more events than counters, the kernel uses time multiplexing. With multiplexing, at the end of the run, the counter is scaled basing on total time enabled vs time running.


Example graph

Graph pmu instructions.png

Instructions (counter) corresponding to perf metric PERF_COUNT_HW_INSTRUCTIONS.

History

  • Cores option is available since release 5.8.1.
  • Support for uncore multi pmu was added in 5.11

Dependencies

See also

Retrieved from "https://collectd.org/wiki/index.php?title=Plugin:Intel_PMU&oldid=5063"