Difference between revisions of "Plugin:Intel PMU"

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     HardwareEvents "L2_RQSTS.CODE_RD_HIT,L2_RQSTS.CODE_RD_MISS" "L2_RQSTS.ALL_CODE_RD"
 
     HardwareEvents "L2_RQSTS.CODE_RD_HIT,L2_RQSTS.CODE_RD_MISS" "L2_RQSTS.ALL_CODE_RD"
 
     Cores "0" "1,35" "[12-17]"
 
     Cores "0" "1,35" "[12-17]"
 +
    DispatchMultiPmu false
 
   </Plugin>
 
   </Plugin>
  

Revision as of 11:07, 16 June 2020

Intel PMU plugin
Type: read
Callbacks: config, init, read, shutdown
Status: supported
First version: 5.8
Copyright: 2017–2018 Intel Corporation
License: MIT license
Manpage: collectd.conf(5)
List of Plugins

The intel_pmu plugin collects information provided by Linux perf interface which provides rich generalized abstractions over hardware specific capabilities. All events are reported on a per core basis.

Performance counters are CPU hardware registers that count hardware events such as instructions executed, cache-misses suffered, or branches mispredicted. They form a basis for profiling applications to trace dynamic control flow and identify hotspots.

For a full description of available options please refer to the collectd.conf(5) manual page.

Synopsis

→ See: Plugin:Intel_PMU/Config
<Plugin intel_pmu>
   ReportHardwareCacheEvents true
   ReportKernelPMUEvents true
   ReportSoftwareEvents true
   EventList "/var/cache/pmu/GenuineIntel-6-2D-core.json"
   HardwareEvents "L2_RQSTS.CODE_RD_HIT,L2_RQSTS.CODE_RD_MISS" "L2_RQSTS.ALL_CODE_RD"
   Cores "0" "1,35" "[12-17]"
   DispatchMultiPmu false
 </Plugin>

For a full description of available options please refer to the collectd.conf(5) manual page.

Example graph

Graph pmu instructions.png

Instructions (counter) corresponding to perf metric PERF_COUNT_HW_INSTRUCTIONS.

History

  • Cores option is available since release 5.8.1.
  • Support for uncore multi pmu was added in 5.11

Dependencies

See also